1. Field of the Invention
The present invention relates to a distributed active transformer (DAT) amplifier with fully differential power combiner.
2. Discussion of the Related Art
Power combiners have particular application in the field of radiofrequency power amplifiers, thanks to the characteristic of in-phase summing the output powers of each individual transistor, maintaining the gain and reducing the voltage thereof at the output terminals.
As is known, in fact, the radiofrequency power amplifier for wireless mobile telecommunications is certainly the most complicated circuit to design using a silicon substrate and using a CMOS compatible process. The reasons for this difficulty are basically two:
1. the breakdown voltages of the gate oxide of the MOS transistor enable rather low RF output powers to be reached; and
2. the quality factor (Q) of the passive elements integrated in the silicon substrate is not suitable for obtaining the high gains and the impedance transformations required by the application specifications of the maximum RF output power.
With the aim of solving the above difficulties, U.S. Pat. No. 6,816,012 and the articles: I. Aoki et al., “Distributed Active Transformer—A new power-combining and impedance-transformation technique”, IEEE Trans. Microwave Theory Tech., Vol. 50, No. 1, January 2002; and I. Aoki et al., “Fully Integrated CMOS PA Design using DAT architecture”, IEEE J. Solid-State Circuits, Vol. 37, No. 3, March 2002 describe a new architecture of impedance transformer and simultaneous power combiner.
FIG. 1 shows the schematic structure of this amplifier 1, comprising four pairs 2 of transistors 3, 4, of an NMOS type, the transistors 3, 4 of each pair 2 having output terminals (drain) connected to four primaries 10 of a distributed active transformer (DAT) 15, proposed herein. The transistors 3, 4 connected across a same primary 10 form a circuit in push-pull configuration.
The primaries 10 are formed by four slabs, here rectangular, each at 90° with respect to the two adjacent slabs so as to extend approximately like the sides of a square. A secondary 16 of the DAT 15 is formed by a region extending substantially along the sides of a square, inside the primaries 10, and a side thereof (on the right in the drawing) is interrupted approximately in the middle and is connected to a pair of outputs 18, supplying a differential output voltage Vo.
The intermediate taps of the primaries 10 are connected to a supply voltage VDD. The transistors 3, 4 of each pair 2 are connected, via the drain terminals, between pairs of adjacent primaries 10 and receive, on the respective gate terminals (which define respective input terminals), voltages of opposite sign. The common node between the source terminals of the two transistors 3, 4 of each pair is grounded.
Tuning capacitors 7 extend between the drain terminals of each pair 2 of transistors 3, 4.
In the known scheme, the secondary 16 of the transformer combines in series, via magnetic induction, the differential signal of the primaries 10 and sends it to the output 18. The advantages of this known transformer structure are the following:                the inductances with high quality factor Q are provided by metal strips instead of by spiral inductors, typically with low Q in the standard CMOS processes;        the transformer ratio of each individual transformer is very low, in other words the ratio is 1:1, and consequently it is simple to obtain and inherently has low ohmic losses;        the total transformer ratio required for increasing the output power of each single pair of MOS transistors is obtained via the in series combination of the voltage induced magnetically on the secondary 16; in FIG. 1, this ratio is 1:4.        
FIG. 2 shows a practical embodiment of the structure object of U.S. Pat. No. 6,816,012 referred to above, in particular in the case of a 2.4-GHz power amplifier having an output power of 1.9 W at a 2 V supply.
As may be noted, the amplifier 1 has a double star structure 20 for biasing the gate terminals of the transistors 3, 4. The double star structure 20 is formed within the secondary 16 in order to contain the ohmic losses as much as possible and consequently reduce the lengths of the metal paths. In detail, the double star structure 20 is formed by a first and a second star regions 20a 20b, formed on two separate metal levels and having each four arms 21a, 21b. The arms 21a of the first star region 20a are connected to the transistors 3, and the arms 21b of the second star region 20b are connected to the transistors 4. In particular, each arm 21a, 21b is connected to a respective transistor 3, 4 via wire connections or further metal levels (represented schematically and designated by 22) that extend under or over the secondary 16. Each star region 20a, 20b further comprises a respective input arm 22a, 22b, connected to an input transformer 25 arranged outside the DAT amplifier 1 and having input terminals receiving a supply voltage Vi and output terminals connected each to a respective input arm 22a, 22b through wire connections or metal lines 26 extending over or under the secondary 16 (and possibly over or under one of the primaries 10).
The gate terminals of the transistors 3, 4 are biased through appropriate biasing regions 28, which are substantially L-shaped, the central tap whereof is a signal virtual ground.
This structure reaches, up to now, the highest power value by using NMOS transistors formed using standard CMOS process, but is not free from disadvantages.
The circular structure of the secondary 16 (which combines the output powers of the pairs of transistors 3, 4) renders in fact very complicated the design of the network needed for connecting the gate terminals of the transistors 3, 4. In fact:                It is difficult to form the network for distributing the RF signal through the double star structure 20 such so as to reduce the parasitic components of resistance, inductance, and capacitance. Therefore, the maximum use frequencies of the DAT 15 and consequently the possible applications are markedly limited;        The input impedance matching network to obtain maximum power transfer to the gate terminals of the transistors 3, 4 is difficult to design in particular for wide frequency bandwidths;        The connection network (double star structure 20) is formed within the secondary 16 of the DAT 15, where the magnetic intensity flux is high. It is consequently very complicated to control coupling between the output and input RF power with consequent problems of stability and oscillation risk; in fact, the star structure is magnetically coupled to the secondary 16 and generates feedback that can cause oscillations;        Extending the double star structure 20 to applications at high frequencies up to the millimetric range becomes impracticable.        
The aim of the present invention is thus to provide an amplifier of the DAT type that overcomes the drawbacks of the prior art.